ICS97ULP845A
Overview
- Low skew, low jitter PLL clock driver
- 1 to 5 differential clock distribution (SSTL_18)
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Auto PD when input signal is at a certain logic state Switching Characteristics:
- Period jitter: 40ps
- Half-period jitter: 60ps
- CYCLE - CYCLE jitter 40ps
- OUTPUT - OUTPUT skew: 40ps
