DESCRIPTION
A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz. The output frequency is an integer multiple of the input reference frequency. The multiplying factor is programmed via a 6 bit parallel address. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. The bandwidth control, low phase noise, and HOLD features make the M2004-02 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in OC-3 through OC-192 applications. FEATURES
Output Clock Frequency up to 700MHz Internal Low-jitter SAW-based Oscillator Intrinsic Jitter <1ps rms (12kHz - 20MHz) Differential Input Compatible with LVPECL, LVDS, HSTL, SSTL, etc. Dual Input MUX Parallel Programming Tunable Loop Filter Response Differential LVPECL Outputs 3.3V Operation Small 9mm x 9mm SMT Package APPLICATIONS
SONET / SDH / 10GbE System Synchronization Add / Drop Muxes,...