MK2302S-01 Datasheet | ICS

Features - - - - - - - - - - - - 8 pin SOIC package Low input to output skew of 250ps max Absolute jitter ± 500ps Propagation Delay ± 350ps Ability to choose between different multipliers from 0.5X to 16X Output clock frequency up to 133 MHz at 3.3V Can recover degraded input clock duty cycle Output clock duty cycle of 45/55 Full CMOS clock swings with 25m A drive capability at TTL levels Advanced, low power CMOS process Operating voltage of 3.3V or 5V Industrial temperature version available Description The MK2302S-01is a high performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. The chip is part of ICS’ Clock Blocks TM family and was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The MK2302S-01 is ideal for synchronizing outputs in a large variety of systems, from personal puters to data munications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices. Block Diagram IC L K S 1 :0 F B IN d ivid e by N P h a se D e te cto r, C h a rg e Pum p, and Loop F ilte r VCO /2 C LK1 C LK2 E x te rn a l fe e d b a ck c a n co m e fro m C L K 1 o r C L K 2 (se e ta b le o n p a g e 2 ) MDS 2302S-01 B Revision 070803 Integrated Circuit Systems, Inc. - 525 Race Street, San Jose, CA 95126 - tel (408) 295-9800 - .icst. .. MK2302S-01 Multiplier and Zero Delay Buffer Pin Assignment FBIN ICLK GND S0 1 2 3 4 8 7 6 5 CLK2 VDD CLK1 S1 8 pin (150 mil) SOIC Clock Multiplier Decoding Table 1 (Multiplies Input clock by shown amount) FBIN CLK1 CLK1 CLK1 CLK1 CLK2 CLK2 CLK2 CLK2 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 CLK1 2 X ICLK 4 X ICLK...