IC41C16256 Datasheet | ICSI

IC41C16256 IC41LV16256 Document Title 256Kx16 bit Dynamic RAM with EDO Page Mode Revision History Revision No 0A 0B 0C History Initial Draft Revise for typo on page 20 Add Pb-free package Draft Date Remark August 9,2001 December 18,2001 April 23,2004 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR018-0C 04/23/2004 IC41C16256 IC41LV16256 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE Features Extended Data-Out (EDO) Page Mode access cycle TTL patible inputs and outputs; tristate I/O Refresh Interval: 512 cycles /8 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden - Single power supply: 5V ± 10% (IC41C16256) 3.3V ± 10% (IC41LV16256) - Byte Write and Byte Read operation via two CAS - Industrail Temperature Range -40o C to 85o C - Pb-free package is available - - - - DESCRIPTION The ICSI IC41C16256 and IC41LV16256 is a 262,144 x 16- bit high-performance CMOS Dynamic Random Access Memories. The IC41C16256 offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IC41C16256 ideal for use in 16-, 32-bit wide data bus systems. These Features make the IC41C16256and IC41LV16256 ideally suited for high-bandwidth graphics, digital signal processing, high-performance puting systems, and peripheral applications. The IC41C16256 is packaged in a 40-pin 400mil SOJ and 400mil TSOP-2. KEY TIMING PARAMETERS Parameter Max. RAS Access Time (t RAC) Max. CAS Access Time (t CAC) Max. Column Address Access Time (t AA) Min. EDO Page Mode Cycle Time (t PC) Min. Read/Write Cycle Time (t RC) -25(5V) 25 8 12 10 45 -35 35 10 18 12 60 -50 50 14 25 20 90 -60 60 15 30 25...