ICS542 - Clock Divider

Product Overview

ICST

Part number	ICS542
Manufacturer	ICST
File Size	76.44 KB
Description	Clock Divider
Datasheet	ICS542 Datasheet
Additional preview pages of the ICS542 datasheet.

The ICS542 is a cost effective way to produce a high quality clock output divided from a clock input.

The chip accepts a clock input up to 156 MHz, and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock.

There are two outputs on the chip, one being a low-skew divide by two of the other.

Packaged as 8 pin SOIC.
ICS’ lowest cost clock divider.
Low skew (500ps) outputs. One is ÷ 2 of other.
Easy to use with other generators and buffers.
Input clock frequency up to 156 MHz.
Output clock duty cycle of 45/55.
Power Down turns off chip.
Output Enable.
Advanced, low power CMOS process.
Operating voltages of 3.0 to 5.5 V Block Diagram VDD GND 2 S1, S0 Divider and Selection Circuitry Input Clock.

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Other Datasheets by ICST

Published: Feb 7, 2007 |