ICST ICS853031
The ICS853031 is a low skew, high performance 1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL HiPerClockS™ Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS853031 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels.| Part No. | ICS853031 |
|---|---|
| Datasheet | ICS853031 Download |
| Manufacturer |  ICST |
| Description | LVPECL/ECL FANOUT BUFFER |
| Buy | Stock & Price |
FEATURES
● 9 differential 2.5V/3.3V LVPECL/ECL outputs● Selectable differential CLK, nCLK or LVPECL clock inputs
● CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL,
● PCLK, nPCLK supports the following input types: LVPECL, LVDS, CML, SSTL
● Output frequency: 1.6GHz (typical)
● Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK or nPCLK inputs
● Output skew: 20ps (typical)
● Part-to-part skew: 75ps (typical)
● Propagation delay: 875ps (typical)
● LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V
● ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V
● -40°C to 85°C ambient operating temperature
● Lead-Free package available
● Pin compatible with ICS8531-01
GENERAL DESCRIPTION
The ICS853031 has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, LVDS, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
