ICS85356I Datasheet | ICST

.. Integrated Circuit Systems, Inc. 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER Features - High speed differential multiplexer. The device can be configured as a 2:1 multiplexer - Dual 3.3V LVPECL outputs - Selectable differential CLKxx, n CLKxx inputs - CLKxx, n CLKxx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL - Output frequency: 900MHz (typical) GENERAL DESCRIPTION The ICS85356I is a dual 2:1 Differential-to-LVPECL Multiplexer and is a member of the Hi Per Clock STM Hi Per Clock S™ family of High Performance Clock Solutions from ICS. The device has both mon select and individual select inputs. When _SEL is logic High, the CLKxx input pairs will be passed to the output. When _SEL is logic Low, the output is determined by the setting of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1. The differential input has a mon mode range that can accept most differential input types such as LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The ICS85356I can therefore be used as a differential translator to translate almost any differential input type to LVPECL. It can also be used in ECL mode by setting VCC=0V and VEE to -3.0V to - 3.8V. The ICS85356I adds negligible jitter to the input clock and can operate at high frequencies in excess of 900MHz thus making it ideal for use in demanding applications such as SONET, Fibre Channel, 1 Gigabit/10 Gigabit Ethernet. - Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on n CLKxx input - Output skew: 75ps (typical) - Propagation delay: 1.15ns (typical) - LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V - ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V - -40°C to 85°C ambient operating temperature - Lead-Free package available - patible with MC100LVEL56 BLOCK DIAGRAM CLK0A n CLK0A CLK0B n CLK0B SEL0 _SEL SEL1 0 1 Q0 n Q0 PIN ASSIGNMENT CLK0A n CLK0A nc...