PA7536 Datasheet | ICT

mercial/Industrial PA7536 PEEL Array™ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for binatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, plex state-machines - parators, decoders, multiplexers and other wide-gate functions High-Speed mercial and Industrial Versions - As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f MAX) - Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 °C temperatures CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC and PLCC packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special Features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - ICT Win PLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmer General Description The PA7536 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7536 offers versatile logic array architecture with 12 I/O pins, 14 input pins and 36 registers/latches (12 buried logic cells, 12 Input registers/latches and 12 buried registers/latches). Its logic array implements 50 sum-of-products logic functions that share 64 product terms. The PA7536’s logic and I/O cells (LCCs, IOCs) are extremely flexible offering up to three output functions per cell (a total of 36 for all 12 logic cells). Cells are configurable as D,...