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PA7536 - Programmable Electrically Erasable Logic

Datasheet Summary

Description

The PA7536 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology.

PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

Features

  • - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - ICT WinPLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmer General.

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Datasheet preview – PA7536

Datasheet Details

Part number PA7536
Manufacturer ICT
File Size 215.55 KB
Description Programmable Electrically Erasable Logic
Datasheet download datasheet PA7536 Datasheet
Additional preview pages of the PA7536 datasheet.

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    Full PDF Text Transcription

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    Commercial/Industrial PA7536 PEEL Array™ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other wide-gate functions High-Speed Commercial and Industrial Versions - As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX) - Industrial grade available for 4.5 to 5.
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