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5P83908 - High-Performance 1.8V/2.5V/3.3V Crystal Input to LVCMOS Clock Fanout Buffer

This page provides the datasheet information for the 5P83908, a member of the 5P83905 High-Performance 1.8V/2.5V/3.3V Crystal Input to LVCMOS Clock Fanout Buffer family.

Description

The 5P8390x is a high performance, 1-to-4/6/8 crystal input to LVCMOS fanout buffer with output enable pins.

This device accepts a fundamental mode crystal from 10MHz to 40MHz and outputs LVCMOS clocks with best-in-class phase noise performance.

Features

  • a synchronous glitch-free Output Enable function to eliminate any intermediate incorrect output clock cycles when enabling or disabling outputs. It comes in standard TSSOP packages or small QFN packages and can operate from 1.8V to 3.3V supplies. 5P83904 Block Diagram Features.
  • 4/6/8 copies of LVCMOS output clocks with best-in-class phase noise performance.
  • Phase Noise: Offset Noise Power (3.3V).
  • 100Hz: -131 dBc/Hz.
  • 1KHz: -145 dBc/Hz.
  • 10KHz: -154 dBc.

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Datasheet preview – 5P83908

Datasheet Details

Part number 5P83908
Manufacturer IDT
File Size 341.16 KB
Description High-Performance 1.8V/2.5V/3.3V Crystal Input to LVCMOS Clock Fanout Buffer
Datasheet download datasheet 5P83908 Datasheet
Additional preview pages of the 5P83908 datasheet.

📁 Similar Datasheet

Other Datasheets by IDT
  • 5P83904 - High-Performance 1.8V/2.5V/3.3V Crystal Input to LVCMOS Clock Fanout Buffer
  • 5P83905 - High-Performance 1.8V/2.5V/3.3V Crystal Input to LVCMOS Clock Fanout Buffer

Full PDF Text Transcription

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High-Performance 1.8V/2.5V/3.3V Crystal Input to LVCMOS Clock Fanout Buffer with OE 5P8390x DATASHEET Description The 5P8390x is a high performance, 1-to-4/6/8 crystal input to LVCMOS fanout buffer with output enable pins. This device accepts a fundamental mode crystal from 10MHz to 40MHz and outputs LVCMOS clocks with best-in-class phase noise performance. The 5P8390x family (5P83904, 5P83905, and 5P83908) features a synchronous glitch-free Output Enable function to eliminate any intermediate incorrect output clock cycles when enabling or disabling outputs. It comes in standard TSSOP packages or small QFN packages and can operate from 1.8V to 3.3V supplies.
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