79RC32364

79RC32364 Key Features

• Based on MIPS 32 RISC architecture with enhancements
• Scalar 5-stage pipeline minimizes branch and load delays
• 66 Million multiply accumulate (MAC) Mul-Add/second @ 133MHz
• 100 and 133 frequencies x MIPS 32 (ISA) instruction set architecture
• MIPS IV patible conditional move instructions
• MIPS IV superset PREF (prefetch) instruction
• Fast multiplier with atomic multiply-add, multiply-sub
• Count leading zeros/ones instructions x Large, efficient on-chip caches
• Separate 8kB Instruction cache and 2kB Data cache
• 2-way set associative