85352 Datasheet LVPECL Clock Buffer

Manufacturer: IDT

Datasheet Details

The 85352 is a 12 bit, 2-to-1 LVPECL Clock Buffer.

Individual input select controls support independent multiplexer operation from a common clock input source.

Clock inputs accept most standard differential levels.

12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer 85352 Datasheet.

Twelve, 2-to-1 multiplexers with LVPECL outputs.
Selectable differential CLKx, nCLKx input pairs.
CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
Maximum output frequency: 700MHz.
Individual select control for each multiplexer.
Select inputs accept LVCMOS / LVTTL levels.
Propagation delay: 2ns (maximum).
Additive Phase Jitter, RMS: 0.21ps (typical), 3.3V.
Full 3.

Part Number	Description
85356	Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer
8530I-01	1-to-16 Differential-to-3.3V LVPECL Fanout Buffer
85311I	LVPECL/ ECL Fanout Buffer
853S01	2:1 Differential-to-LVPECL Multiplexer
853S011B	LVPECL/ ECL Fanout Buffer
853S058	LVPECL/ECL Clock Multiplexer
853S111B	LVPECL/ECL Fanout Buffer