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854S006I - Differential-to-LVDS Fanout Buffer

Description

The 854S006I is a low skew, high perfor- mance 1-to-6 Differential-to-LVDS Fanout Buffer.

The CLK, nCLK pair can accept most standard differential input levels.

The 854S006I is characterized to operate from either a 2.5V or a 3.3V power supply.

Features

  • Six differential LVDS outputs.
  • One differential clock input pair.
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
  • Maximum output frequency: 1.7GHz.
  • Translates any single ended input signal to LVDS levels with resistor bias on nCLK input.
  • Output skew: 55ps (maximum).
  • Propagation delay: 850ps (maximum).
  • Additive phase jitter, RMS: 0.067ps (typical).
  • Full 3.3V or 2.

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Datasheet Details

Part number 854S006I
Manufacturer IDT
File Size 211.46 KB
Description Differential-to-LVDS Fanout Buffer
Datasheet download datasheet 854S006I Datasheet
Additional preview pages of the 854S006I datasheet.

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Full PDF Text Transcription

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Low Skew, 1-to-6, Differential-toLVDS Fanout Buffer 854S006I Data Sheet GENERAL DESCRIPTION The 854S006I is a low skew, high perfor- mance 1-to-6 Differential-to-LVDS Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The 854S006I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output skew characteristics make the 854S006I ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES • Six differential LVDS outputs • One differential clock input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1.
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