89HPES48T12 Datasheet | IDT

Overview The 89HPES48T12 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES48T12 is a 48-lane, 12-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high-performance applications such as servers, storage, and munications/networking. It provides connectivity and switching functions between a PCI Express upstream port and up to eleven downstream ports and supports switching between downstream ports. - Features - High Performance PCI Express Switch - Twelve switch ports - Six main ports each of which consists of 8 Ser Des - Each x8 main port can further bifurcate to 2 x4-ports - Forty-eight 2.5 Gbps embedded Ser Des - Supports pre-emphasis and receive equalization on per-port basis - Delivers 192 Gbps (24 GBps) of aggregate switching capacity - Low-latency cut-through switch architecture - Support for Max Payload Size up to 2048 bytes - - - Supports one virtual channel and eight traffic classes - PCI Express Base Specification Revision 1.1 pliant Flexible Architecture with Numerous Configuration Options - Port arbitration schemes utilizing round robin algorithms - Automatic per port link width negotiation to x8, x4, x2 or x1 - Automatic lane reversal on all ports - Automatic polarity inversion on all lanes - Supports locked transactions, allowing use with legacy software - Ability to load device configuration from serial EEPROM - Ability to control device via SMBus Highly Integrated Solution - Requires no external ponents - Incorporates on-chip internal memory for packet buffering and queueing - Integrates forty-eight 2.5 Gbps embedded full duplex Ser Des, 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Redundant upstream port failover capability - Supports optional PCI Express end-to-end CRC checking Block Diagram x8/x4/x2/x1 Ser Des DL/Transaction Layer Upstream Route Table Port Arbitration Scheduler 12-Port...