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8P391208 - Low Additive Jitter 2:8 Buffer

Datasheet Summary

Description

8P391208 is intended to take 1 or 2 reference clocks, select between them, using a pin selection and generate up to 8 outputs that are the same as the reference frequency.

8P391208 supports two output banks, each with its own power supply.

Features

  • Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks.
  • Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz (up to 1GHz when configured into HCSL output mode at 3.3V).
  • Select which of the two input clocks is to be used as the reference clock for which bank via pin selection.
  • Generates 8 differential outputs.
  • Differential outputs selectable as LVPECL, LVDS, CML or HCSL.
  • CML mod.

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Datasheet preview – 8P391208

Datasheet Details

Part number 8P391208
Manufacturer IDT
File Size 872.69 KB
Description Low Additive Jitter 2:8 Buffer
Datasheet download datasheet 8P391208 Datasheet
Additional preview pages of the 8P391208 datasheet.

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Full PDF Text Transcription

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Low Additive Jitter 2:8 Buffer with Universal Differential Outputs 8P391208 Datasheet General Description 8P391208 is intended to take 1 or 2 reference clocks, select between them, using a pin selection and generate up to 8 outputs that are the same as the reference frequency. 8P391208 supports two output banks, each with its own power supply. All outputs in one bank would generate the same output frequency, and each bank can be individually controlled for output type or output enable. The device can operate over the -40°C to +85°C temperature range. Features • Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks • Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz (up to 1GHz when configured into HCSL output mode at 3.
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