8P79818 Overview
The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. The 8P79818 supports two output banks, each with its own divider and power supply. All outputs in one bank would generate the same output frequency, but each output can be individually controlled...
8P79818 Key Features
- Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks
- Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz
- Select which of the two input clocks is to be used as the reference clock for which divider via pin or register selectio
- Switchover will not generate any runt clock pulses on the output
- Generates eight differential outputs or eight LVCMOS outputs, Bank A only
- Differential outputs selectable as LVPECL, LVDS, CML or HCSL
- Differential outputs support frequencies from 1PPS to 700MHz
- LVCMOS outputs support frequencies from 1PPS to 200MHz
- LVCMOS outputs in the same pair may be inverted or in-phase relative to one another
- Outputs arranged in 2 banks of 4 outputs each