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9DBL0243 - 2-Output 3.3V LP-HCSL Zero-Delay Buffer

General Description

The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's Full-Featured PCIe clock family.

4 Common Clock (CC) architectures and also support NVLINK applications.

Key Features

  • Loss Of Signal (LOS) open drain output.
  • 2 1.
  • 200 MHz Low-Power (LP) HCSL DIF pairs.
  • 9DBL0243 default Zout = 100Ω.
  • 9DBL0253 default Zout = 85Ω.
  • Easy AC-coupling to other logic families; see IDT.

📥 Download Datasheet

Datasheet Details

Part number 9DBL0243
Manufacturer IDT
File Size 350.15 KB
Description 2-Output 3.3V LP-HCSL Zero-Delay Buffer
Datasheet download datasheet 9DBL0243 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
2-Output 3.3V LP-HCSL Zero-Delay 9DBL0243 / 9DBL0253 Buffer with LOS Indicator Datasheet Description The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's Full-Featured PCIe clock family. They support PCIe Gen1–4 Common Clock (CC) architectures and also support NVLINK applications. The 9DBL0243 / 9DBL0253 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high-reliability systems. Typical Applications ▪ PCIe Gen1–4 and NVLINK clock distribution for Riser Cards ▪ Storage and Networking ▪ JBOD ▪ Communications ▪ Access Points Output Features ▪ Loss Of Signal (LOS) open drain output ▪ 2 1–200 MHz Low-Power (LP) HCSL DIF pairs — 9DBL0243 default Zout = 100Ω — 9DBL0253 default Zout = 85Ω ▪ Easy AC-coupling to other logic families; see IDT application note AN-891.