9DBL07P1 Key Features
- 1-200 MHz Low-Power (LP) HCSL DIF pairs
- 9DBL0741 default Zout = 100Ω
- 9DBL0751 default Zout = 85Ω
- 9DBL07P1 factory programmable defaults
- Easy AC-coupling to other logic families, see IDT
- DIF additive cycle-to-cycle jitter < 5ps
- DIF output-to-output skew < 50ps
- Additive phase jitter is 0p