9DBU0541 Key Features
- DIF additive cycle-to-cycle jitter < 5ps
- DIF output-to-output skew < 60ps
- DIF additive phase jitter is < 300fs rms for PCIe Gen3
- DIF additive phase jitter < 350fs rms for SGMII
- 35mW typical power consumption; eliminates thermal
- Spread Spectrum (SS) patible; allows SS for EMI
- OE# pins; support DIF power management
- HCSL-patible differential input