9DBU0741 - 7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer

IDT

General Description

The 9DBU0741 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family.

It has integrated terminations for direct connection to 100 transmission lines.

The device has 7 output enables for clock management, and 3 selectable SMBus addresses.

Key Features

7.
1-167MHz Low-Power (LP) HCSL DIF pairs w/ZO=100 Key Specifications.
DIF additive cycle-to-cycle jitter.

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9DBU0741 7-output 1.5v pcie gen1-2-3 fanout buffer by IDT - Datasheet Preview

Datasheet Details

Part number	9DBU0741
Manufacturer	IDT
File Size	210.86 KB
Description	7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
Datasheet	9DBU0741 Datasheet

Other Datasheets by IDT

Part Number	Description
9DBU0731	7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
9DBU0231	2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0241	2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0431	4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0441	4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0531	5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
9DBU0541	5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
9DBU0631	6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0641	6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0831	8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer w/Zo=100ohms 9DBU0741 DATASHEET Description The 9DBU0741 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 transmission lines. The device has 7 output enables for clock management, and 3 selectable SMBus addresses. Recommended Application 1.5V PCIe Gen1-2-3 Fan-out Buffer (FOB) Output Features • 7 – 1-167MHz Low-Power (LP) HCSL DIF pairs w/ZO=100 Key Specifications • DIF additive cycle-to-cycle jitter <5ps • DIF output-to-output skew < 60ps • DIF additive phase jitter is <300fs rms for PCIe Gen3 • DIF additive phase jitter <350s rms for SGMII Block Diagram vOE(6:0)# 7 CLK_IN CLK_IN# vSADR ^CKPWRGD_PD# SDATA_3.3 SCLK_3.