9DBU0831 Key Features
- 1-167MHz Low-Power (LP) HCSL DIF pairs
- DIF cycle-to-cycle jitter <50ps
- DIF output-to-output skew < 75ps
- DIF phase jitter is PCIe Gen1-2-3 pliant
- LP-HCSL outputs; save 16 resistors pared to standard
- 53mW typical power consumption in PLL mode; eliminates
- Outputs can optionally be supplied from any voltage
- Spread Spectrum (SS) patible; allows SS for EMI