9DBU0931 Key Features
- 1-167MHz Low-Power (LP) HCSL DIF pairs
- DIF additive cycle-to-cycle jitter <5ps
- DIF output-to-output skew < 60ps
- DIF additive phase jitter is <300fs rms for PCIe Gen 3
- DIF additive phase jitter <350fs rms for SGMII
- LP-HCSL outputs; save 18 resistors pared to standard
- 47mW typical power consumption in PLL mode; minimal
- Outputs can optionally be supplied from any voltage
- Spread Spectrum (SS) patible; allows SS for EMI
- OE# pins for each output; support DIF power management