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ICS853S12I - LVPECL FANOUT BUFFER

Description

Clock Solutions from IDT.

The PCLK, nPCLK pair accepts LVPECL, CML, and SSTL differential input levels.

Features

  • Twelve differential 3.3V, 2.5V LVPECL outputs.
  • PCLK, nPCLK input pair.
  • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL.
  • Maximum output frequency: 1.5GHz.
  • Translates any single-ended input signal to 2.5V or 3.3V.

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Datasheet preview – ICS853S12I

Datasheet Details

Part number ICS853S12I
Manufacturer IDT
File Size 249.60 KB
Description LVPECL FANOUT BUFFER
Datasheet download datasheet ICS853S12I Datasheet
Additional preview pages of the ICS853S12I datasheet.

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Full PDF Text Transcription

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LOW SKEW, 1-TO-12, DIFFERENTIAL-TO3.3V, 2.5V LVPECL FANOUT BUFFER ICS853S12I GENERAL DESCRIPTION The ICS853S12I is a low skew, 1-to-12 DifferentialICS to-3.3V, 2.5V LVPECL Fanout Buffer and a member HiPerClockS™ of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The PCLK, nPCLK pair accepts LVPECL, CML, and SSTL differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV, as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the ICS853S12I ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES • Twelve differential 3.3V, 2.
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