Datasheet4U Logo Datasheet4U.com

ICS8735I-21 - ZERO DELAY CLOCK GENERATOR

General Description

The ICS8735I-21 is a highly versatile 1:1 Differential-to3.3V LVPECL clock generator.

The CLK, nCLK pair can accept most standard differential input levels.

Key Features

  • One differential 3.3V LVPECL output pair, one differential feedback output pair.
  • Differential CLK, nCLK input pair.
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
  • Output frequency range: 31.25MHz to 700MHz.
  • Input frequency range: 31.25MHz to 700MHz.
  • VCO range: 250MHz to 700MHz.
  • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2.

📥 Download Datasheet

Datasheet Details

Part number ICS8735I-21
Manufacturer IDT
File Size 248.78 KB
Description ZERO DELAY CLOCK GENERATOR
Datasheet download datasheet ICS8735I-21 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS8735-01 ZERO DELAY CLOCK GENERATOR Integrated Circuit Systems
ICS8735-21 ZERO DELAY CLOCK GENERATOR Integrated Circuit Systems
ICS87354I CLOCK GENERATOR Integrated Circuit Systems
ICS873032 5V LVPECL/ECL CLOCK GENERATOR Integrated Circuit System
ICS873033 3.3V 5V LVPECL/ECL CLOCK GENERATOR Integrated Circuit Systems

Other Datasheets by IDT

Part Number Description
ICS87002-05 1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer
ICS87004I Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator
ICS87008I 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS874S02I 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS87973I-147 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ICS8735I-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR GENERAL DESCRIPTION The ICS8735I-21 is a highly versatile 1:1 Differential-to3.3V LVPECL clock generator. The CLK, nCLK pair can accept most standard differential input levels. The ICS8735I-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes.