IDT70V3569S Datasheet | IDT

.. HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features : x x IDT70V3569S x x x x True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access - mercial: 4.2/5/6ns (max.) - Industrial: 5/6ns (max) Pipelined output mode Counter enable and reset Features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports - 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) - Fast 4.2ns clock to data out - 1.8ns setup to clock and 0.7ns hold on all control, data, and x x x x x address inputs @ 133MHz - Data input, address, byte enable and control registers - Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching patibility LVTTL- patible, single 3.3V (±150m V) power supply for core LVTTL- patible, selectable 3.3V (±150m V)/2.5V (±125m V) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available for selected speeds Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-ball fine-pitch Ball Grid Array, and 256-pin Ball Grid Array Functional Block Diagram BE3L BE3R BE2L BE1L BE0L BE2R BE1R BE0R R/WL B W 0 L B W 1 L B W 2 L B B WW 3 3 L R BB WW 2 1 RR B W 0 R R/WR CE0L CE1L CE0R CE1R Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R 16K x 36 MEMORY ARRAY I/O0L- I/O35L Din_L Din_R I/O0R - I/O35R CLKL A13L A0L CNTRSTL ADSL...