IDT70V658 Datasheet | IDT

HIGH-SPEED 3.3V IDT70V659/58/57S 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM LEAD FINISH (Sn Pb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features - True Dual-Port memory cells which allow simultaneous access of the same memory location - High-speed access - mercial: 10/12/15ns (max.) - Industrial: 12/15ns (max.) - Dual chip enables allow for depth expansion without external logic - IDT70V659/58/57 easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device - M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave - Busy and Interrupt Flags - On-chip port arbitration logic - Full on-chip hardware support of semaphore signaling between ports - Fully asynchronous operation from either port - Separate byte controls for multiplexed bus and bus matching patibility - Supports JTAG Features pliant to IEEE 1149.1 - LVTTL-patible, single 3.3V (±150m V)...