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IDT70V9359L - HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

Download the IDT70V9359L datasheet PDF. This datasheet also covers the IDT70V9359 variant, as both devices belong to the same high-speed 3.3v 8/4k x 18 synchronous pipelined dual-port static ram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • True Dual-Ported memory cells which allow simultaneous access of the same memory location.
  • High-speed clock to data access.
  • Commercial: 6.5/7.5/9ns (max. ).
  • Industrial: 7.5ns (max. ).
  • Low-power operation.
  • IDT70V9359/49L Active: 450mW (typ. ) Standby: 1.5mW (typ. ).
  • Flow-Through or Pipelined output mode on either port via the FT/PIPE pins.
  • Counter enable and reset features.
  • Dual chip enables allow for depth expansion without additional logic.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT70V9359-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT70V9359L
Manufacturer IDT
File Size 186.73 KB
Description HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Datasheet download datasheet IDT70V9359L Datasheet

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Other Datasheets by IDT

Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70V9359/49L Features: ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 6.5/7.5/9ns (max.) – Industrial: 7.5ns (max.) ◆ Low-power operation – IDT70V9359/49L Active: 450mW (typ.) Standby: 1.5mW (typ.) ◆ Flow-Through or Pipelined output mode on either port via the FT/PIPE pins ◆ Counter enable and reset features ◆ Dual chip enables allow for depth expansion without additional logic Functional Block Diagram ◆ Full synchronous operation on both ports – 3.5ns setup to clock and 0ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 6.