IDT72261LA Description
CMOS SuperSync FIFO™ 16,384 x 9 IDT72261LA 32,768 x 9 IDT72271LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018.
IDT72261LA Key Features
- Pin-patible with the IDT72281/72291 SuperSync FIFOs
- 10ns read/write cycle time (8ns access time)
- Fixed, low first word data latency time
- Auto power down minimizes standby power consumption
- Master Reset clears entire FIFO
- Partial Reset clears data, but retains programmable settings
- Retransmit operation with fixed, low first word data latency time
- Empty, Full and Half-Full flags signal FIFO status
- Programmable Almost-Empty and Almost-Full flags, each flag
- Program partial flags by either serial or parallel means