IDT72265LA Datasheet PDF - IDT CMOS FIFO memories Specs

IDT72265LA - CMOS FIFO memories

This page provides the datasheet information for the IDT72265LA, a member of the IDT72255LA CMOS FIFO memories family.

Datasheet Summary

Features

Choose among the following memory organizations: IDT72255LA.
8,192 x 18 IDT72265LA.
16,384 x 18.
Pin-compatible with the IDT72275/72285 SuperSync FIFOs.
10ns read/write cycle time (8ns access time).
Fixed, low first word data latency time.
Auto power down minimizes standby power consumption.
Master Reset clears entire FIFO.
Partial Reset clears data, but retains programmable settings.
Retransmit operation.

Datasheet Details

Part number	IDT72265LA
Manufacturer	IDT
File Size	208.46 KB
Description	CMOS FIFO memories
Datasheet	IDT72265LA Datasheet
Additional preview pages of the IDT72265LA datasheet.

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Full PDF Text Transcription

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CMOS SuperSync FIFO™ 8,192 x 18 IDT72255LA 16,384 x 18 IDT72265LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES • Choose among the following memory organizations: IDT72255LA — 8,192 x 18 IDT72265LA — 16,384 x 18 • Pin-compatible with the IDT72275/72285 SuperSync FIFOs • 10ns read/write cycle time (8ns access time) • Fixed, low first word data latency time • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Retransmit operation with fixed, low first word data latency time • Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets • Program partial

Published: Apr 6, 2019 |