IDT72265LA Datasheet | IDT

CMOS Super Sync FIFO™ 8,192 x 18 IDT72255LA 16,384 x 18 LEAD FINISH (Sn Pb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features - Choose among the following memory organizations: IDT72255LA - 8,192 x 18 IDT72265LA - 16,384 x 18 - Pin-patible with the IDT72275/72285 Super Sync FIFOs - 10ns read/write cycle time (8ns access time) - Fixed, low first word data latency time - Auto power down minimizes standby power consumption - Master Reset clears entire FIFO - Partial Reset clears data, but retains programmable settings - Retransmit operation with fixed, low first word data latency time - Empty, Full and Half-Full flags signal FIFO status - Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets - Program partial flags by either serial or parallel means - Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) - Output...