IDT72V2101 Overview
3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO™ 262,144 x 9 IDT72V2101 524,288 x 9 IDT72V2111 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15,.
IDT72V2101 Key Features
- Pin-patible with the IDT72V261/72V271 and the IDT72V281/ 72V291 SuperSync FIFOs
- 10ns read/write cycle time (6.5ns access time)
- Fixed, low first word data latency time
- 5V input tolerant
- Auto power down minimizes standby power consumption
- Master Reset clears entire FIFO
- Partial Reset clears data, but retains programmable settings
- Retransmit operation with fixed, low first word data latency time
- Empty, Full and Half-Full flags signal FIFO status
- Programmable Almost-Empty and Almost-Full flags, each flag can