IDT74SSTU32865 Overview
All clock and data inputs are patible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load.
IDT74SSTU32865 Key Features
- Available in 160-pin CTBGA package
IDT74SSTU32865 Applications
- Along with CSPU877/A/D DDR2 PLL, provides plete solution for DDR2 DIMMs
- Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D