IDT74SSTU32D869
Overview
This device supports low-power s.
- 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Center input architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
- Available in 150-pin CTBGA package
