Datasheet4U Logo Datasheet4U.com

IDT74SSTUAE32866A - 25-BIT CONFIGURABLE REGISTERED BUFFER

General Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation.

The control inputs are LVCMOS.

All outputs are 1.5-V CMOS drivers that have been optimized to drive the DDR-II DIMM load.

Key Features

  • Supports 1.5V VDD operation for DDR2 DIMMs.
  • 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check.
  • functionality Supports LVCMOS switching levels on C0, C1, and RESET inputs Low voltage operation: VDD = 1.425V to 1.575V Available in 96-ball LFBGA package.

📥 Download Datasheet

Datasheet Details

Part number IDT74SSTUAE32866A
Manufacturer IDT
File Size 666.82 KB
Description 25-BIT CONFIGURABLE REGISTERED BUFFER
Datasheet download datasheet IDT74SSTUAE32866A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER Renesas
IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE Integrated Device Tech
IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER Renesas
IDT74ALVC162245 3.3V CMOS 16-BIT BUS TRANSCEIVER Integrated Device Tech
IDT74ALVC162334 16-bit universal bus driver Renesas

Other Datasheets by IDT

Part Number Description
IDT74SSTUA32866 1.8V CONFIGURABLE BUFFER
IDT74SSTU32864 1:1 AND 1:2 REGISTERED BUFFER
IDT74SSTU32864A 1:1 AND 1:2 REGISTERED BUFFER
IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER
IDT74SSTU32866B 1.8V CONFIGURABLE BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUAE32866A outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC). Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.