IDT74SSTUB32866B Overview
This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. In the 1:1 pinout configuration, only one device per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive eighteen SDRAM loads.
IDT74SSTUB32866B Key Features
- 400 / 533 / 667 / 800 (PC2
- 3200 / 4300 / 5300 / 6400) JEDEC R/C E, F, G, H, and J Available in 96-pin LFBGA package
IDT74SSTUB32866B Applications
- Along with CSPUA877 DDR2 PLL, provides plete solution for DDR2 DIMMs