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IDT74SSTV16857 - 14-BIT REGISTERED BUFFER

Datasheet Summary

Description

The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V VDD and supports low standby operation.

All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2.

RESET is an LVCMOS input since it must operate predictably during the power-up phase.

Features

  • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM loads Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0).
  • Available in TSSOP package.

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Datasheet preview – IDT74SSTV16857

Datasheet Details

Part number IDT74SSTV16857
Manufacturer IDT
File Size 81.70 KB
Description 14-BIT REGISTERED BUFFER
Datasheet download datasheet IDT74SSTV16857 Datasheet
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www.DataSheet4U.com IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O IDT74SSTV16857 FEATURES: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM loads Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Available in TSSOP package DESCRIPTION: The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V VDD and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2.
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