Datasheet Details
| Part number | SSTE32882KA1 |
|---|---|
| Manufacturer | IDT |
| File Size | 1.17 MB |
| Description | 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER |
| Datasheet |
 SSTE32882KA1 Datasheet
|
|
|
General Description
This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.
All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS.
Key Features
- Pinout optimizes DDR3 RDIMM PCB layout.
- DDR3-800/1066/1333/1600/1866/2133 rate.
- 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs.
- Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs.
- Supports LVCMOS switching levels on the RESET and MIRROR inputs.
- Checks priority on DIMM-independent data inputs.
- Supports dynamic 1T/3T timing.