IN16C554A Overview
IN16C554A Quadruple UART February 2009 REV 1.01 IN16C554A is an enhanced quadruple version of the 16C550UART (Universal Asynchronous Receiver Transmitter). IN16C554A is in part an upgrade version of IN16C554, as it is designed for 3.3V only and has AUTO-CTS, AUTO-RTS functions. In IN16C554A, Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead.
IN16C554A Key Features
- In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the number of interrup
- Adds or deletes standard asynchronous munication bits (start, stop, parity) to or from the serial data
- Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial data
- Independently controlled transmit, receive, line status and data interrupts
- Programmable Baud Rate Generators which allow division of any input reference
- Independent receiver clock input
- Fully programmable serial interface characteristics
- 5-, 6-, 7-, or 8-bit characters
- Even-, Odd-, or No-Parity bit 1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, IN16C554 checks only one stop
- False start bit detection