IN74AC109 - Dual J-K Positive-Edge-Triggered Flip-Flop

IK Semiconductor

Datasheet Details

Part number	IN74AC109
Manufacturer	IK Semiconductor
File Size	305.72 KB
Description	Dual J-K Positive-Edge-Triggered Flip-Flop
Datasheet	IN74AC109 Datasheet

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IN74AC10	Triple 3-Input Positive-NAND Gate
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TECHNICAL DATA IN74AC109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high transition of the clock. Both Q to Q outputs are available from each flip-flop. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA; 0.