IW4023B
TECHNICAL DATA
Triple 3-Input NAND Gate
High-Voltage Silicon-Gate CMOS
The IW4023B NAND gates provide the system designer with direct emplementation of the NAND function.
- Operating Voltage Range: 3.0 to 18 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 n A at 18 V and 25°C
- Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
ORDERING INFORMATION IW4023BN Plastic IW4023BD SOIC TA = -55° to 125° C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
FUNCTION TABLE
PIN 14 =VCC PIN 7 = GND Inputs A L X X H B X L X H C X X L H Output Y H H H L w w w
.d e e h s a t a
. u t4 m o c
X = don’t care
..
MAXIMUM RATINGS-
Symbol VCC VIN VOUT IIN PD PD Tstg TL
- Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC...
