IW4029B
TECHNICAL DATA
Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS
The IW4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. ORDERING INFORMATION A low on each JAM line, when the PRESET-ENABLE signal is high, IW4029BN Plastic resets the counter to its zero count. The counter is advanced one count at IW4029BD SOIC the positive transition of the clock when the CARRY IN and PRESET TA = -55° to 125° C for all packages ENABLE signals are low. Advancement is inhibited when the CARRY IN or PRESET ENABLE signals are high. The CARRY OUT signal is normally high and goes low when...
