Datasheet Details
| Part number | PZ5032-10A44 |
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| Manufacturer | INTEGRATED CIRCUIT ENGINEERING |
| File Size | 5.50 MB |
| Description | 32 Macrocell PLD |
| Datasheet |
 PZ5032-10A44 Datasheet
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General Description
Assembly Die Process ANALYSIS RESULTS I Assembly ANALYSIS RESULTS II Die Process TABLES Procedure Overall Quality Evaluation Package Markings Wirebond Strength Die Material Analysis Horizontal Dimensions Vertical Dimensions
PAGE 1 1
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-iFree Datasheet http://www.Da
Key Features
- Twin-well CMOS process in an N substrate (no epi).
- Sub-micron gate lengths (0.35 micron N-channel and 0.4 micron P-channel).
- Tungsten plugs used under all metal layers. 1These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended.