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IS25WD040 - 2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory

This page provides the datasheet information for the IS25WD040, a member of the IS25WD020 2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory family.

Description

The IS25WD020/040 are 2 Mbit / 4Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output.

The devices are designed to support a 30 MHz fclock rate in normal read mode, and 80 MHz in fast read, the fastest in the industry.

Features

  • Single Power Supply Operation - Low voltage range: 1.65 V.
  • 1.95 V.
  • Memory Organization - IS25WD020: 256K x 8 (2 Mbit) - IS25WD040: 512K x 8 (4 Mbit).
  • Cost Effective Sector/Block Architecture - 2Mb : Uniform 4KByte sectors / Four uniform 64KByte blocks - 4Mb : Uniform 4KByte sectors / Eight uniform 64KByte blocks.
  • Serial Peripheral Interface (SPI) Compatible - Supports single- or dual-output - Supports SPI Modes 0 and 3 - Maximum 30 MHz clock rate fo.

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Datasheet preview – IS25WD040

Datasheet Details

Part number IS25WD040
Manufacturer ISSI (now Infineon)
File Size 669.81 KB
Description 2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory
Datasheet download datasheet IS25WD040 Datasheet
Additional preview pages of the IS25WD040 datasheet.

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Full PDF Text Transcription

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IS25WD020/040 2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory With 80 MHz Dual-Output SPI Bus Interface FEATURES • Single Power Supply Operation - Low voltage range: 1.65 V – 1.95 V • Memory Organization - IS25WD020: 256K x 8 (2 Mbit) - IS25WD040: 512K x 8 (4 Mbit) • Cost Effective Sector/Block Architecture - 2Mb : Uniform 4KByte sectors / Four uniform 64KByte blocks - 4Mb : Uniform 4KByte sectors / Eight uniform 64KByte blocks • Serial Peripheral Interface (SPI) Compatible - Supports single- or dual-output - Supports SPI Modes 0 and 3 - Maximum 30 MHz clock rate for normal read - Maximum 80 MHz clock rate for fast read • Page Program (up to 256 Bytes) Operation - Typical 2 ms per page program • Sector, Block or Chip Erase Operation - Typical 1.
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