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IS42S16800B - 8Meg x16 128-MBIT SYNCHRONOUS DRAM

General Description

A0-A11 A0-A9 BA0, BA1 DQ0 to DQ7 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM VDD Vss VDDQ VssQ NC Write Enable Data Input/Output Mask Power Ground P

Key Features

  • Clock frequency: 167, 143, 133 MHz.
  • Fully synchronous; all signals referenced to a positive clock edge.
  • Internal bank for hiding row access/precharge.
  • Power supply IS42S81600B IS42S16800B.
  • LVTTL interface.
  • Programmable burst length.
  • (1, 2, 4, 8, full page) www. DataSheet4U. com.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS42S16800A 128-MBIT SYNCHRONOUS DRAM Integrated Circuit Solution
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IS42S16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM Integrated Silicon Solution
IS42S16128 128K words x 16 Bits x 2 Banks SDRAM Integrated Silicon
IS42S16160 16Meg x16 256-MBIT SYNCHRONOUS DRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS42S16800D 128-MBIT SYNCHRONOUS DRAM
IS42S16800F 128Mb SYNCHRONOUS DRAM
IS42S16100A1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16100F 512K Words x 16 Bits x 2 Banks 16Mb SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS42S81600B IS42S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM ISSI MAY 2006 ® FEATURES • Clock frequency: 167, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S81600B IS42S16800B • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) www.DataSheet4U.com OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. VDDQ VDD 3.3V 3.3V 3.3V 3.