IS42S16800F Datasheet | ISSI

IS42/45S81600F IS42/45S16800F 16Mx8, 8Mx16 128Mb SYNCHRONOUS DRAM SEPTEMBER 2019 Features - Clock frequency: 200, 166, 143 MHz - Fully synchronous; all signals referenced to a positive clock edge - Internal bank for hiding row access/precharge - Power supply Vdd Vddq IS42/45S81600F 3.3V 3.3V IS42/45S16800F 3.3V 3.3V - LVTTL interface - Programmable burst length - (1, 2, 4, 8, full page) - Programmable burst sequence: Sequential/Interleave - Auto Refresh (CBR) - Self Refresh - 4096 refresh cycles every 16 ms (A2 grade) or 64 ms (mercial, Industrial, A1 grade) - Random column address every clock cycle - Programmable CAS latency (2, 3 clocks) - Burst read/write and burst read/single write operations capability - Burst termination by burst stop and precharge mand - Temperature Ranges: mercial (0o C to +70o C) Industrial (-40o C to +85o C) Automotive, A1 (-40o C to +85o C) Automotive, A2 (-40o C to +105o C) OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized as follows. IS42/45S81600F IS42/45S16800F 4M x8 x4 Banks 2M x16 x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball...