IS42VM16160M - 4M x 16Bits x 4Banks Mobile Synchronous DRAM
ISSI (now Infineon)
Download the IS42VM16160M datasheet PDF.
This datasheet also covers the IS45VM16160M variant, as both devices belong to the same 4m x 16bits x 4banks mobile synchronous dram family and are provided as variant models within a single manufacturer datasheet.
General Description
These IS42/45VM16160G are mobile 268,435,456 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 16 bits.
These products are offering fully synchronous operation and are referenced to a positive edge of the clock.
Key Features
JEDEC standard1.8V power supply.
Auto refresh and self refresh.
All pins are compatible with LVCMOS interface.
8K refresh cycle every 16ms (A2 grade) or 64ms (Industrial, A1 grade).
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst.
Programmable CAS Latency : 2,3 clocks.
All inputs and outputs referenced to the positive edge of the system clock.
Full PDF Text Transcription for IS42VM16160M (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
IS42VM16160M. For precise diagrams, and layout, please refer to the original PDF.
IS42/45VM16160M 4M x 16Bits x 4Banks Mobile Synchronous DRAM Preliminary Information Description These IS42/45VM16160G are mobile 268,435,456 bits CMOS Synchronous DRAM o...
View more extracted text
se IS42/45VM16160G are mobile 268,435,456 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features ▪ JEDEC standard1.
IS42VM16160M Datasheet
