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IS43R16320F - 512Mb DDR SDRAM

Download the IS43R16320F datasheet PDF. This datasheet also covers the IS46R86400F variant, as both devices belong to the same 512mb ddr sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

x8 A0-A12 Row Add

Key Features

  • VDD and VDDQ: 2.5V ± 0.2V (-5, -6).
  • VDD and VDDQ: 2.5V ± 0.1V (-4).
  • SSTL_2 compatible I/O.
  • Double-data rate architecture; two data transfers per clock cycle.
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs.
  • Differential clock inputs (CK and CK).
  • DLL aligns DQ and DQS transitions.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS46R86400F-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS43R16320A 32Meg x 16 512-MBIT DDR SDRAM Integrated Silicon Solution
IS43R16320D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Integrated Silicon Solution
IS43R16320E 512Mb DDR SDRAM Integrated Silicon Solution
IS43R16160 256Mb Synchronous DRAM Integrated Silicon Solution
IS43R16160A 16Meg x 16 256-MBIT DDR SDRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS43R16160B 256Mb DDR Synchronous DRAM
IS43R16160D DDR SDRAM
IS43R16400B Four internal banks for concurrent operation
IS43R32800D DDR SDRAM
IS43R32800D DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS43/46R86400F IS43/46R16320F ® Long-term Support World Class Quality 32Mx16, 64Mx8 JANUARY 2020 512Mb DDR SDRAM FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data Mask for write data.