IS46LR32640A Datasheet | ISSI

Description The IS43/46LR32640A is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 33,554,432 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are patible with LVCMOS. Features - JEDEC standard 1.8V power supply. - VDD = 1.8V, VDDQ = 1.8V - Four internal banks for concurrent operation - MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8) - Burst type (sequential & interleave) - Fully differential clock inputs (CK, /CK) - All inputs except data & DM are sampled at the rising edge of the system clock - Data I/O transaction on both edges of data strobe - Bidirectional data strobe per byte of data (DQS) - DM for write masking only - Edge aligned data & data strobe output - Center aligned data & data strobe input - 64ms refresh period (8K cycle) - Auto & self refresh - Concurrent Auto Precharge - Maximum clock frequency up to 200MHZ - Maximum data rate up to 400Mbps/pin - Power Saving support - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature pensated Self Refresh) - Deep Power Down Mode - Programmable Driver Strength Control by Full Strength or 1/2, 1/4, or 1/8 of Full Strength - LVCMOS patible inputs/outputs - 90-Ball FBGA package - 64Mx32 (two stacked 16Mx16x4 banks) Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability...