IS46R16160D Overview
IS43R83200D IS43/46R16160D, IS43/46R32800D JUNE 2012 8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM.
IS46R16160D Key Features
- VDD and VDDQ: 2.5V ± 0.2V
- SSTL_2 patible I/O
- Double-data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
- Differential clock inputs (CK and CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Four internal banks for concurrent operation
- Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
