Datasheet4U Logo Datasheet4U.com

IS61DDB24M18C - 72Mb DDR-II CIO SYNCHRONOUS SRAM

General Description

The 72Mb IS61DDB22M36C and IS61DDB24M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • Common I/O read and write ports.
  • Max. 400 MHz clock for high bandwidth.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two input clocks (C and C#) for data output contro.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDB24M18 DDR-II (Burst of 2) CIO Synchronous SRAMs Integrated Silicon Solution
IS61DDB24M18A 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDB21M18A 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDB21M36 DDR-II (Burst of 2) CIO Synchronous SRAMs Integrated Silicon Solution
IS61DDB21M36A 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDB22M36C 72Mb DDR-II CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C2 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61DDB24M18C IS61DDB22M36C 4Mx18, 2Mx36 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  Common I/O read and write ports.  Max. 400 MHz clock for high bandwidth  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.  HSTL input and output interface.