IS61DDB24M18C Datasheet | ISSI

IS61DDB24M18C IS61DDB22M36C 4Mx18, 2Mx36 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM APRIL 2018 Features - 2Mx36 and 4Mx18 configuration available. - mon I/O read and write ports. - Max. 400 MHz clock for high bandwidth - Synchronous pipeline read with self-timed late write operation. - Double Data Rate (DDR) interface for read and write input ports. - Fixed 2-bit burst for read and write operations. - Clock stop support. - Two input clocks (K and K#) for address and control registering at rising edges only. - Two input clocks (C and C#) for data output control. - Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. - +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF. - HSTL input and output interface. - On-chip delay-locked loop (DLL) for wide data valid window. - Full data coherency. - Boundary scan using limited set of JTAG 1149.1 functions. - Byte write capability. - Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array - Programmable impedance output drivers via 5x user-supplied precision resistor. DESCRIPTION The 72Mb IS61DDB22M36C and IS61DDB24M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a mon I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write mand signal, and the second burst is timed to the following...