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IS61LPS25632T - 256Kx32 Synchronous Pipelined Static RAM

Download the IS61LPS25632T datasheet PDF. This datasheet also covers the IS61SPS25632D variant, as both devices belong to the same 256kx32 synchronous pipelined static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

IS61LPS25632, IS61LPS25636, and IS61LPS51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance memory for communication and networking applications.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Linear burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • JEDEC 100-Pin TQFP and 119-pin PBGA package.
  • Single +3.3V, +10%,.
  • 5% power supply.
  • Power-down snooze mode.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61SPS25632D_ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61LPS25618A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS25672A 18Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS204818A 36Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS102418B SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS102436A 36Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61LPS25632A Single CYCLE DESELECT STATIC RAM
IS61LPS25632B 9Mb Single CYCLE DESELECT STATIC RAM
IS61LPS25632D 256Kx32 Synchronous Pipelined Static RAM
IS61LPS25636A Single CYCLE DESELECT STATIC RAM
IS61LPS25636B 9Mb Single CYCLE DESELECT STATIC RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61SPS25632T/D IS61LPS25632T/D IS61SPS25636T/D IS61LPS25636T/D IS61SPS51218T/D IS61LPS51218T/D 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, SINGLE-CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Linear burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +3.3V, +10%, –5% power supply • Power-down snooze mode • 3.3V I/O For SPS • 2.