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IS61LPS51218A - Single CYCLE DESELECT STATIC RAM

General Description

IS64LPS25636A and IS61LPS/VPS51218A are highspeed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth ex- pansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boun.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS61LPS51236A 18Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS51236B SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS102418B SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS102436A 36Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS12832A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61LPS51218B 9Mb Single CYCLE DESELECT STATIC RAM
IS61LPS51218D 256Kx32 Synchronous Pipelined Static RAM
IS61LPS51218T 256Kx32 Synchronous Pipelined Static RAM
IS61lPS102418A 18Mb Single CYCLE DESELECT STATIC RAM
IS61LPS102436B 36Mb Single CYCLE DESELECT STATIC RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM JANUARY 2014 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for BGA package • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.